The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

May. 29, 2019
Applicant:

Nutanix, Inc., San Jose, CA (US);

Inventors:

Mohammad Mahmood, Bangalore, IN;

Anoop Menon, Bangalore, IN;

Ashwin Thennaram Vakkayil, Malappuram, IN;

Sandeep Kumar Madanala, Hyderabad, IN;

Shubham Shukla, Bangalore, IN;

Chern Yih Cheah, Seattle, WA (US);

Assignee:

Nutanix, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01);
Abstract

A method commences upon accessing a set of data items that describe computing nodes to be organized into failure-tolerant configuration. The failure-tolerant configuration is characterized by system availability characteristics such as a replication factor and such as a hierarchical distribution of computing nodes. Characteristics of the topology include boundaries that define two or more hierarchically-related availability domain levels. Computing nodes are situated within these boundaries. Instances of a target hierarchical availability domain level are sorted, and instances of a hierarchically lower availability domain level are also sorted to form a multi-level sort order of computing nodes. Computing entities are mapped onto the computing nodes by observing the multi-level sort order.


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