The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jul. 05, 2018
Applicants:

Imec Vzw, Leuven, BE;

Katholieke Universiteit Leuven, Leuven, BE;

Inventors:

Francky Catthoor, Temse, BE;

Praveen Raghavan, Los Gatos, CA (US);

Daniele Garbin, Leuven, BE;

Dimitrios Rodopoulos, Leuven, BE;

Odysseas Zografos, Leuven, BE;

Assignees:

IMEC vzw, Leuven, BE;

Katholieke Universiteit Leuven, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); G06N 3/063 (2006.01); G11C 17/16 (2006.01); G11C 11/54 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0646 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 7/1006 (2013.01); G11C 11/54 (2013.01); G11C 13/0002 (2013.01); G11C 13/0061 (2013.01); G11C 16/04 (2013.01); G11C 17/165 (2013.01); G06N 3/088 (2013.01); G11C 2213/71 (2013.01);
Abstract

A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.


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