The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Dec. 27, 2018
Applicant:

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventor:

Yanxi Ye, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/1368 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13624 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136209 (2013.01); G02F 1/136286 (2013.01); H01L 27/1248 (2013.01); G02F 1/134363 (2013.01); G02F 1/136227 (2013.01); G02F 2001/133357 (2013.01); G02F 2001/134345 (2013.01); G02F 2001/136222 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

A display panel and manufacturing method for the same. The display panel includes an array substrate, a passivation layer, an organic planarization layer, a first color resist layer and a second color resist layer and an organic planarization layer. Each sub-pixel circuit includes at least two thin-film transistors; at least two via holes are prepared on the passivation layer and the organic planarization layer. The first color resist layer includes a first color resist region and multiple second color resist regions connected thereto. A projection of the first color resist region on the array substrate is located at two sides of the sub-pixel circuit. Each second color resist region is located above the at least two thin-film transistors; the second color resist layer is stacked above the second color resist region. The first color resist layer will not crack, and the main region spacer can reach a desired height.


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