The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Nov. 22, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Matthew S. Doyle, Chatfield, MN (US);

Joseph Kuczynski, North Port, FL (US);

Phillip V. Mann, Rochester, MN (US);

Kevin M. O'Connell, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01); H01L 21/311 (2006.01); H01L 23/48 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H05K 3/425 (2013.01); H05K 1/034 (2013.01); H05K 1/115 (2013.01); H05K 3/423 (2013.01); H05K 2201/015 (2013.01); H05K 2203/143 (2013.01);
Abstract

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.


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