The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Feb. 14, 2017
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Yuhang Liu, Lund, SE;

Joakim Axmon, Limhamn, SE;

Michael Breschel, Lund, SE;

Johan Hill, Lund, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 5/00 (2006.01); H03M 1/12 (2006.01); H03M 1/46 (2006.01); H04B 1/16 (2006.01); H04L 27/26 (2006.01);
U.S. Cl.
CPC ...
H04L 5/0007 (2013.01); H03M 1/1255 (2013.01); H03M 1/46 (2013.01); H04B 1/16 (2013.01); H04L 27/2647 (2013.01);
Abstract

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.


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