The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Jul. 31, 2018
Applicant:
Altera Corporation, San Jose, CA (US);
Inventor:
Tony K. Ngai, Saratoga, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H01L 25/065 (2006.01); H03K 19/17736 (2020.01); G06F 30/39 (2020.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017581 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H03K 19/017509 (2013.01); H03K 19/17744 (2013.01); G06F 30/39 (2020.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.