The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Aug. 27, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Changkyo Lee, Suwon-si, KR;

Dongkeon Lee, Suwon-si, KR;

Jinhoon Jang, Suwon-si, KR;

Kyungsoo Ha, Suwon-si, KR;

Kiseok Oh, Suwon-si, KR;

Kyungryun Kim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); H03K 19/0175 (2006.01); H03K 19/018 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0005 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G11C 7/1051 (2013.01); G11C 7/1084 (2013.01); H03K 19/01825 (2013.01); H03K 19/017545 (2013.01);
Abstract

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.


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