The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jun. 28, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Mihir Mudholkar, Tempe, AZ (US);

Mohammed T. Quddus, Chandler, AZ (US);

Ikhoon Shin, Pocatello, ID (US);

Scott M. Donaldson, Pocatello, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/872 (2013.01); H01L 29/0619 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/66143 (2013.01); H01L 29/8725 (2013.01); H01L 29/16 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01);
Abstract

A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g., reduced leakage and more stable breakdown voltage) and improved reliability.


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