The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Mar. 05, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Seokhwan Bang, Yongin-si, KR;

Soojung Chae, Seoul, KR;

Kapsoo Yoon, Seoul, KR;

Woogeun Lee, Yongin-si, KR;

Sunghoon Lim, Suwon-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42384 (2013.01); H01L 27/1237 (2013.01); H01L 29/42364 (2013.01); H01L 29/517 (2013.01); H01L 29/6675 (2013.01); H01L 29/7869 (2013.01);
Abstract

A thin film transistor substrate includes: a substrate; an oxide semiconductor layer disposed on the substrate; a gate electrode disposed on the substrate; a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode; and a source electrode and a drain electrode connected to the oxide semiconductor layer, the source electrode and the drain electrode being spaced apart from each other. The gate insulating layer includes: a first gate insulating layer having an oxygen content lower than that of a stoichiometric composition; and a second gate insulating layer including a material substantially the same as a material which the first gate insulating layer may include, and having an oxygen content higher than that of the first gate insulating layer, and the first gate insulating layer and the oxide semiconductor layer directly contact each other.


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