The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Apr. 19, 2017
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventor:
Toshitake Yaegashi, Yokohama, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11563 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/11568 (2017.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/517 (2013.01); H01L 29/792 (2013.01);
Abstract
A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.