The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Dec. 14, 2018
Applicant:

Gio Optoelectronics Corp, Tainan, TW;

Inventor:

Chin-Tang Li, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 27/12 (2006.01); H01L 33/52 (2010.01); H01L 33/62 (2010.01); H01L 21/48 (2006.01); H01L 33/00 (2010.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/486 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 25/50 (2013.01); H01L 27/124 (2013.01); H01L 33/0095 (2013.01); H01L 33/52 (2013.01); H01L 33/62 (2013.01); H01L 24/97 (2013.01); H01L 25/167 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/81205 (2013.01); H01L 2224/81805 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/97 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0066 (2013.01);
Abstract

An electronic package unit, a manufacturing method thereof and an electronic device are disclosed. The manufacturing method includes: providing an insulation substrate, wherein the insulation substrate has a first surface and a second surface opposite to the first surface; forming a plurality of sub-matrix circuits on the insulation substrate, wherein each sub-matrix circuit comprises at least one thin film transistor; disposing at least one functional chip on the first surface, wherein the functional chip is electrically connected with the sub-matrix circuit; forming a plurality of through-holes on the insulation substrate and disposing a conductive material in the through-holes, so that the functional chip is electrically connected to the second surface through the sub-matrix circuits and the conductive material; forming a protection layer on the first surface to cover the functional chips; and cutting the insulation substrate and the protection layer to form a plurality of electronic package units.


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