The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Sep. 04, 2018
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Liang Shi, Chongqing, CN;

Yejia Di, Chongqing, CN;

Hsing Mean Sha, Chongqing, CN;

Yuangang Wang, Shenzhen, CN;

Dongfang Shan, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 29/52 (2006.01); G11C 11/56 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3418 (2013.01); G06F 11/1068 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01); G11C 16/3431 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01); G11C 11/5635 (2013.01); H01L 29/788 (2013.01);
Abstract

A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.


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