The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Sep. 04, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Masashi Yamaoka, Yokohama, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/24 (2006.01); H01L 27/1158 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/24 (2013.01); H01L 27/1157 (2013.01); H01L 27/1158 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.


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