The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Dec. 23, 2019
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Seung Wook Oh, Yongin-si, KR;

Young Suk Seo, Seoul, KR;

Da In Im, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); H03K 5/135 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1066 (2013.01); G11C 7/222 (2013.01); G11C 8/10 (2013.01); H03K 5/135 (2013.01);
Abstract

A semiconductor apparatus includes a clock path, a command path, a delay monitoring circuit, and an output control circuit. The clock path generates a delay clock signal by delaying a clock signal. The command path generates an output command signal from on one of a command signal and the clock signal, based on a monitoring signal. The delay monitoring circuit generates a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled. The output control circuit generates an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.


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