The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Mar. 21, 2016
Emc Corporation, Hopkinton, MA (US);
Robert Guowu Xia, Shanghai, CN;
Joseph James Longever, Jr., Dorchester, MA (US);
Simon Alexander Jensen-Fellows, Acton, MA (US);
Xiaoxia Shu, Shanghai, CN;
Xiaoguang Fu, Shanghai, CN;
Chao Wang, Shanghai, CN;
Xingwang Cai, Shanghai, CN;
Chao Wu, Shanghai, CN;
Xin Lin, Shanghai, CN;
EMC IP Holding Company LLC, Hopkinton, MA (US);
Abstract
Techniques for building and implementing computing systems with simulated hardware infrastructures are provided to support, for example, development and testing of management and orchestration software. For example, a system includes a processing platform comprising hardware resources, and a simulated computing system executing on top of the processing platform using the hardware resources. The simulated computing system comprises simulated elements including a simulated compute node, a simulated network switch device, and a simulated power distribution device. The simulated compute node comprises a simulated hardware processor and a simulated storage device. The system further comprises a test control interface configured to enable a user to test the simulated computing system by injecting an error into the simulated computing system. For example, error injection includes manipulating a behavior of one or more of the simulated elements and/or simulating a failure of one or more of the simulated elements.