The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Apr. 21, 2018
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Jeremy Fowers, Seattle, WA (US);

Kalin Ovtcharov, Issaquah, WA (US);

Eric S. Chung, Woodinville, WA (US);

Todd Michael Massengill, Woodinville, WA (US);

Ming Gang Liu, Kirkland, WA (US);

Gabriel Leonard Weisz, Bethesda, MD (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 3/0613 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 9/3001 (2013.01); G11C 7/1078 (2013.01); G11C 8/16 (2013.01);
Abstract

Neural network processors including a vector register file (VRF) having a multi-port memory and related methods are provided. The processor may include tiles to process an N by N matrix of data elements and an N by 1 vector of data elements. The VRF may, in response to a write instruction, store N data elements in a multi-port memory and during each one of out of P clock cycles provide N data elements to each one of P input interface circuits of the multi-port memory comprising an input lane configured to carry L data elements in parallel. During the each one of the P clock cycles the multi-port memory may be configured to receive N data elements via a selected at least one of the P input interface circuits. The VRF may include output interface circuits for providing N data elements in response to a read instruction.


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