The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jul. 03, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chad M. Albertson, Rochester, MN (US);

Eric J. Campbell, Rochester, MN (US);

Nicholas J. Ollerich, Rochester, MN (US);

Christopher W. Steffen, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/14 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); H05K 1/115 (2013.01); H05K 3/0014 (2013.01); H05K 3/146 (2013.01); H05K 3/3405 (2013.01); H05K 3/3436 (2013.01); H05K 2201/09636 (2013.01); H05K 2201/09836 (2013.01); H05K 2201/09945 (2013.01); Y10T 29/49155 (2015.01);
Abstract

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.


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