The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jul. 30, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Pedro W. Neto, Douglas, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/466 (2013.01); H03M 1/462 (2013.01);
Abstract

Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.


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