The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Mar. 27, 2020
Applicant:

The Boeing Company, Chicago, IL (US);

Inventors:

Alfio Zanchi, Seattle, WA (US);

Parham Khajeh Hesamaddin, Irvine, CA (US);

Assignee:

The Boeing Company, Chicago, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03L 7/087 (2006.01); H03L 7/23 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); H03L 7/087 (2013.01); H03L 7/0993 (2013.01); H04L 7/033 (2013.01); H03L 7/23 (2013.01);
Abstract

A clock data recovery circuit is disclosed. The clock data recovery circuit includes a bit stream data rate divider and a digital phase-locked loop including a linear phase detector. The bit stream data rate divider is configured to divide a frequency of a serial data stream by a designated division factor to generate a divided serial data stream. The linear phase detector is configured to compare phases of the divided serial data stream and a feedback signal within the digital phase-locked loop and output an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream. The digital phase-locked loop is configured to output a clock signal having a phase based on a digital difference between a digitized-UP signal derived from the UP signal and a digitized-DOWN signal derived from the DOWN signal.


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