The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Jul. 23, 2018
Applicant:
X Development Llc, Mountain View, CA (US);
Inventors:
Michial Allen Gunter, Oakland, CA (US);
Charles Henry Leichner, IV, Palo Alto, CA (US);
Tammo Spalink, Mountain View, CA (US);
Assignee:
X Development LLC, Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06N 3/04 (2006.01); H03K 19/17736 (2020.01); G06N 3/08 (2006.01); G06N 3/063 (2006.01); H03K 19/0175 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17744 (2013.01); G06F 15/8046 (2013.01); G06F 15/8053 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/082 (2013.01); H03K 19/017509 (2013.01); H03K 19/017545 (2013.01); H03K 19/017581 (2013.01); H03K 19/1774 (2013.01); G06F 2015/763 (2013.01);
Abstract
An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.