The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jan. 07, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Yiching Chen, San Jose, CA (US);

Thomas G. Mckay, Boulder Creek, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03G 3/30 (2006.01); H03F 3/213 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0216 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03G 3/3042 (2013.01); H03F 2200/18 (2013.01); H03F 2200/451 (2013.01);
Abstract

Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.


Find Patent Forward Citations

Chen, Yiching. (2020). Circuit structure to generate back-gate voltage bias for amplifier circuit, and related method (U.S. Patent No. 10790785). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10790785

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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