The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jun. 25, 2019
Applicant:

Gachon University of Industry-academic Cooperation Foundation, Seongnam-si, Gyeonggi-do, KR;

Inventors:

Seongjae Cho, Seoul, KR;

EunSeon Yu, Seoul, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/122 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/165 (2013.01); H01L 29/42344 (2013.01); H01L 29/7926 (2013.01);
Abstract

An intelligent semiconductor device has a body region in which a channel is formed. The body region has a heterojunction of different semiconductor layers and a quantum well formed in a semiconductor layer in contact with a drain. The quantum well is configured to store holes generated in a depletion layer of the drain region and imitate a short-term memory, and to convert the short-term memory into a long-term memory by enabling holes to be injected into a charge storage layer when the holes stored in quantum well exceed a specific threshold value. It is possible to fabricate with a bulk semiconductor substrate and utilize the conventional CMOS technology.


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