The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Mar. 11, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Mikihiko Ito, Tokyo, JP;

Masaru Koyanagi, Tokyo, JP;

Masafumi Nakatani, Tokyo, JP;

Masahiro Yoshihara, Yokohama, JP;

Shinya Okuno, Yokohama, JP;

Shigeki Nagasaka, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01); H01L 27/10 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01); H01L 27/10 (2013.01); G11C 16/0483 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01);
Abstract

According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.


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