The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

May. 21, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jiseok Hong, Yongin-si, KR;

Chan-Sic Yoon, Anyang-si, KR;

Ilyoung Moon, Yongin-si, KR;

Jemin Park, Suwon-si, KR;

Kiseok Lee, Hwaseong-si, KR;

Jung-Hoon Han, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/76804 (2013.01); H01L 21/76814 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01);
Abstract

A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.


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