The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Feb. 28, 2018
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Sambhrama Mundkur, Sammamish, WA (US);

Fengfen Liu, Sammamish, WA (US);

Norman Lam, Sammamish, WA (US);

Andrew Putnam, Seattle, WA (US);

Somesh Chaturmohta, Redmond, WA (US);

Daniel Firestone, Seattle, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/801 (2013.01); G06F 15/173 (2006.01); H04L 29/06 (2006.01); G06F 9/455 (2018.01); G06F 15/76 (2006.01); H04L 12/813 (2013.01); H04L 12/935 (2013.01); H04L 12/931 (2013.01); H04L 12/46 (2006.01); H04L 12/911 (2013.01); H04L 12/861 (2013.01); H04L 12/707 (2013.01); H04L 12/721 (2013.01); H04L 12/717 (2013.01); H04L 12/741 (2013.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 15/17331 (2013.01); G06F 9/45533 (2013.01); G06F 9/45558 (2013.01); G06F 15/76 (2013.01); H04L 12/4641 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/54 (2013.01); H04L 47/193 (2013.01); H04L 47/20 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/741 (2013.01); H04L 47/822 (2013.01); H04L 49/3027 (2013.01); H04L 49/3045 (2013.01); H04L 49/354 (2013.01); H04L 49/9068 (2013.01); H04L 69/12 (2013.01); H04L 69/22 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45595 (2013.01); H04L 49/70 (2013.01); H04L 67/10 (2013.01); H04L 67/1097 (2013.01); H04L 69/161 (2013.01);
Abstract

Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array ('FPGA') that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.


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