The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Dec. 04, 2018
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G06F 12/0882 (2016.01); G06F 12/02 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0882 (2013.01); G06F 12/0246 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7203 (2013.01);
Abstract
A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.