The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Oct. 30, 2017
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Roberto Pio Baorda, Binasco, IT;

Paolo Angelini, Bologna, IT;

Danilo Karim Kaddouri, Pero, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); G05F 3/26 (2006.01); H03F 3/345 (2006.01); H03H 11/02 (2006.01); H03F 3/45 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0416 (2013.01); G05F 3/262 (2013.01); H03F 3/345 (2013.01); H03F 3/45273 (2013.01); H03H 11/025 (2013.01); G06F 3/044 (2013.01); G06F 2203/04104 (2013.01); H03F 2200/91 (2013.01);
Abstract

A differential current conveyor circuit includes two or more single-ended current conveyor stages and a common bias stage. First and second switches are set between the control terminals of the transistors in the common bias stage and a respective one of a first and a second coupling line of the single ended stages can be switched between the following: a reset state of the circuit with the transistors in the common bias stage coupled to the first and second coupling lines with the single-ended stages set to a bias condition; and a sensing state of the circuit with the transistors in the common bias stage decoupled from the first and second coupling lines, with the single-ended stages in a high impedance state with the control terminals of the input transistors of the single ended stages capacitively coupled to the input terminal.


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