The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Mar. 12, 2018
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:
Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 25/02 (2006.01); G01R 31/382 (2019.01); H01M 10/42 (2006.01); G06F 13/40 (2006.01); H04L 29/12 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
H04L 25/0278 (2013.01); G01R 31/382 (2019.01); G06F 13/4022 (2013.01); H01M 10/425 (2013.01); H04L 25/0266 (2013.01); H04L 25/0272 (2013.01); G06F 13/4086 (2013.01); G06F 13/4247 (2013.01); H01M 2010/4271 (2013.01); H01M 2010/4278 (2013.01); H04L 61/2038 (2013.01);
Abstract

Aspects of the present disclosure are directed to facilitating communications to respective circuit nodes in a manner that may also be useful for mitigating undesirable signal attenuation. As may be implemented in accordance with one or more embodiments, switchable isolation circuits, presented by at least one transformer and switch, are utilized to isolate adjacent data processing nodes on a bus in which each data processing node includes logic circuitry and processes signal therein. For each of the switchable isolation circuits, switching circuitry operates to mitigate communication propagation over the differential bus between adjacent data processing nodes, by switching the switchable isolation circuit for providing isolation. This approach may be utilized, for example, to assign sequential identification to daisy-chained circuit nodes upon start-up or reset, for use in addressing each node directly for further communication therewith.


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