The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
May. 10, 2019
State Grid Jiangsu Electric Power Co., Ltd, Nanjing, Jiangsu, CN;
Nari Technology Co., Ltd, Nanjing, Jiangsu, CN;
Jijun Yin, Jiangsu, CN;
Qing Chen, Jiangsu, CN;
Zheng Wu, Jiangsu, CN;
Xiao Lu, Jiangsu, CN;
Hengzhi Cui, Jiangsu, CN;
Jianyu Luo, Jiangsu, CN;
Chunlei Xu, Jiangsu, CN;
Xueming Li, Jiangsu, CN;
Xiangdong Chen, Jiangsu, CN;
Kaiming Luo, Jiangsu, CN;
Bijun Li, Jiangsu, CN;
Lin Liu, Jiangsu, CN;
Yunsong Yan, Jiangsu, CN;
Jianfeng Ren, Jiangsu, CN;
Haifeng Xia, Jiangsu, CN;
State Grid Jiangsu Electric Power Co., Ltd., Nanjing, Jiangsu, CN;
Nari Technology Co., Ltd., Nanjing, Jiangsu, CN;
Abstract
Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus.