The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

May. 01, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Minoru Kurosawa, Tokyo, JP;

Kichiya Itagaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02P 6/182 (2016.01); H02P 21/22 (2016.01); H02K 5/24 (2006.01);
U.S. Cl.
CPC ...
H02P 6/182 (2013.01); H02K 5/24 (2013.01); H02P 21/22 (2016.02);
Abstract

The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN_to REGN_for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.


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