The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Mar. 05, 2018
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

William George Mahoney, Suwanee, GA (US);

John Alexander Ritchie, Jr., Duluth, GA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02G 3/03 (2006.01); H05K 5/02 (2006.01); H02G 3/08 (2006.01); H05K 7/20 (2006.01); H04B 1/16 (2006.01); H04B 1/04 (2006.01); H02G 3/14 (2006.01);
U.S. Cl.
CPC ...
H02G 3/03 (2013.01); H02G 3/083 (2013.01); H02G 3/14 (2013.01); H05K 5/02 (2013.01); H02G 3/086 (2013.01); H02G 3/088 (2013.01); H04B 1/04 (2013.01); H04B 1/16 (2013.01); H05K 7/20409 (2013.01); H05K 7/20418 (2013.01);
Abstract

A three-piece electronics enclosure may be provided. The electronics enclosure may comprise a back housing, a lid, and a center frame. The back housing may comprise back housing heat sinks on an exterior of the back housing and back housing circuitry disposed in an interior of the back housing. The lid may comprise lid heat sinks on an exterior of the lid and lid circuitry disposed in an interior of the lid. The center frame may be disposed between the back housing and the lid. The center frame may comprise a plurality of input/output (I/O) ports comprising a first I/O port and a second I/O port. At least one of the plurality of I/O ports may provide power to the back housing circuitry and the lid circuitry. The center frame may further comprise a power bypass that passes power between the first I/O port and the second I/O port.


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