The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Feb. 21, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Xiaoxiong Gu, White Plains, NY (US);

Wooram Lee, Briarcliff Manor, NY (US);

Duixian Liu, Scarsdale, NY (US);

Christian Wilhelmus Baks, Pleasant Valley, NY (US);

Alberto Valdes-Garcia, Chappaqua, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01Q 1/22 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01); H01Q 23/00 (2006.01); H01Q 21/00 (2006.01); H01Q 21/06 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); H01L 23/3675 (2013.01); H01L 23/66 (2013.01); H01L 24/16 (2013.01); H01Q 21/0093 (2013.01); H01Q 21/061 (2013.01); H01Q 23/00 (2013.01); H05K 1/181 (2013.01); H01L 24/13 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6633 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15173 (2013.01); H01L 2924/15321 (2013.01); H05K 2201/1053 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10734 (2013.01);
Abstract

Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.


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