The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Apr. 09, 2019
Applicant:

3-5 Power Electronics Gmbh, Dresden, DE;

Inventor:

Volker Dudek, Ettlingen, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/861 (2006.01); H01L 29/34 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/32 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 21/18 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8613 (2013.01); H01L 29/0607 (2013.01); H01L 29/0657 (2013.01); H01L 29/0661 (2013.01); H01L 29/20 (2013.01); H01L 29/32 (2013.01); H01L 29/34 (2013.01); H01L 29/36 (2013.01); H01L 29/66204 (2013.01); H01L 21/187 (2013.01);
Abstract

A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a pregion, an nlayer, and an nregion. The pregion, the nlayer, and the nregion follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The nregion or the pregion is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the nlayer or of an intermediate layer adjacent to the nlayer and to the pregion and the first and the second peripheral edges each have a width of at least 10 μm.


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