The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Nov. 06, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-oh Kim, Daegu, KR;

Ki-seok Lee, Hwaseong-si, KR;

Chan-sic Yoon, Anyang-si, KR;

Je-min Park, Suwon-si, KR;

Woo-song Ahn, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/538 (2006.01); H01L 29/49 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); H01L 23/538 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10852 (2013.01); H01L 27/10876 (2013.01); H01L 27/10894 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 21/26513 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/3081 (2013.01); H01L 29/6656 (2013.01);
Abstract

An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.


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