The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Nov. 30, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Pawan Garg, Munich, DE;

Mathias Kiele-Dunsche, Neubiberg, DE;

Tomas Manuel Reiter, Munich, DE;

Christopher Roemmelmayer, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/40 (2006.01); H01L 23/498 (2006.01); H01L 21/52 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4006 (2013.01); H01L 21/52 (2013.01); H01L 23/49838 (2013.01); H01L 23/544 (2013.01); H01L 2023/4087 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface.


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