The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Apr. 29, 2019
Applicant:

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Wuhan, Hubei, CN;

Inventor:

Heng Liu, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76813 (2013.01); H01L 21/76804 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 27/1469 (2013.01); H01L 27/14636 (2013.01); H01L 27/14689 (2013.01);
Abstract

A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.


Find Patent Forward Citations

Liu, Heng. (2020). Method of making an interconnection between wafers after wafer level stacking, based on 3d-ic technology (U.S. Patent No. 10784152). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10784152

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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