The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Jul. 10, 2019
Applicants:

Toyota Motor Engineering & Manufacturing North America, Inc., Plano, TX (US);

The Board of Trustees of the Leland Stanford Junior University, Stanford, CA (US);

Inventors:

Feng Zhou, South Lyon, MI (US);

Ki Wook Jung, Santa Clara, CA (US);

Ercan Mehmet Dede, Ann Arbor, MI (US);

Mehdi Asheghi, Palo Alto, CA (US);

Kenneth E. Goodson, Portola Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); B81C 1/00 (2006.01); H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); B81C 1/00396 (2013.01); B81C 1/00412 (2013.01); B81C 1/00523 (2013.01); B81C 1/00531 (2013.01); B81C 1/00563 (2013.01); B81C 1/00603 (2013.01); H01L 21/3081 (2013.01); H01L 23/34 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0135 (2013.01);
Abstract

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.


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