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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10783981 B1

PDFFull Text
Date of Patent:
Sep. 22, 2020

Filed:

Apr. 04, 2018

Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same

Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Sang-Hyun Ban, Icheon, KR;

Tae-Hoon Kim, Seongnam, KR;

Woo-Tae Lee, Seoul, KR;

Hye-Jung Choi, Icheon, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:

J H Hur

Int. Cl.
CPC ...
G11C 29/50 (2006.01); H01L 27/22 (2006.01); G11C 11/16 (2006.01); H01L 45/00 (2006.01); H01L 43/08 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); G06F 12/0802 (2016.01); H01L 23/528 (2006.01); G11C 29/04 (2006.01); H01L 43/10 (2006.01); H01F 10/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50 (2013.01); G06F 12/0802 (2013.01); G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); H01L 23/528 (2013.01); H01L 27/222 (2013.01); H01L 27/2463 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/5004 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01L 43/10 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the first lines and the second lines and coupled between the first lines and the second lines, the plurality of memory cells having a first turn-on voltage; and a test circuit block suitable for applying a stress pulse having a voltage level equal to or higher than the first turn-on voltage to one or more first lines selected from the first lines in a test mode.

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