The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

May. 03, 2019
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Chun-Yi Tu, Hsinchu County, TW;

Ming-Chang Tsai, Hsinchu County, TW;

Jui-Lung Weng, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 29/52 (2006.01); G11C 16/10 (2006.01); G11C 5/14 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 5/147 (2013.01); G11C 11/5621 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 29/52 (2013.01);
Abstract

A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.


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