The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
Apr. 21, 2020
Applicant:
Toshiba Memory Corporation, Tokyo, JP;
Inventors:
Fumiyoshi Matsuoka, Kawsaki Kanagawa, JP;
Katsuyuki Fujita, Nishitokyo Tokyo, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 5/02 (2006.01); G11C 11/34 (2006.01); G11C 5/06 (2006.01); G11C 7/02 (2006.01); G11C 11/16 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
G11C 5/14 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/02 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 11/1693 (2013.01); G11C 11/1697 (2013.01); G11C 11/34 (2013.01); G11C 27/024 (2013.01); G11C 2207/105 (2013.01);
Abstract
A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.