The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Aug. 21, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yanru Li, San Diego, CA (US);

Azzedine Touzni, Carlsbad, CA (US);

Dexter Chun, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 21/57 (2013.01); G06F 9/445 (2018.01); G06F 9/4401 (2018.01); G06F 21/51 (2013.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 1/3206 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 9/4401 (2013.01); G06F 9/4403 (2013.01); G06F 9/4418 (2013.01); G06F 9/44557 (2013.01); G06F 9/44573 (2013.01); G06F 9/44578 (2013.01); G06F 15/781 (2013.01); G06F 21/51 (2013.01);
Abstract

System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.


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