The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Jul. 27, 2017
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

Yi-Lin Lai, New Taipei, TW;

Chen-Te Chen, New Taipei, TW;

Ying-Che Chung, New Taipei, TW;

Assignee:

VIA Technologies, Inc., New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/29 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1004 (2013.01); G06F 11/1048 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); H03M 13/09 (2013.01); H03M 13/1102 (2013.01); H03M 13/152 (2013.01);
Abstract

A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.


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