The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Jan. 20, 2017
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Shigetaka Mori, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/26 (2006.01); G01R 27/02 (2006.01); G01R 31/00 (2006.01); G01R 29/24 (2006.01); G01R 31/01 (2020.01); G01R 31/28 (2006.01); G01N 27/22 (2006.01); H03K 5/15 (2006.01);
U.S. Cl.
CPC ...
G01R 27/2605 (2013.01); G01N 27/22 (2013.01); G01R 27/02 (2013.01); G01R 29/24 (2013.01); G01R 31/001 (2013.01); G01R 31/016 (2013.01); G01R 31/2822 (2013.01); G01R 31/2853 (2013.01); H03K 5/15 (2013.01);
Abstract

The present disclosure relates to a semiconductor integrated circuit and a signal processing method that can improve measurement accuracy. Pulses subjected to pulse generation and disconnection control by a control circuit are supplied to a pulse distribution circuit and a CP circuit. The pulse distribution circuit divides one pulse into two or more pulses that do not overlap each other, and supplies the pulses to a CBCM circuit. The CBCM circuit is configured by connecting a capacitance element to be measured to the output of a measurement core circuit called a pseudo inverter. The CP circuit inputs, to the gate electrode, pulses that cause a channel of a non-measurement MISFET to change from the accumulation state to the inverted state, and monitors, from the substrate side, a CP current flowing through a trap acting as a recombination center of the gate insulating film and the semiconductor substrate interface. The present disclosure can be applied to, for example, a semiconductor integrated circuit for evaluating the characteristics of the gate insulating film of the MISFET.


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