The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Jul. 27, 2018
Applicant:
Nippon Mektron, Ltd., Tokyo, JP;
Inventor:
Fumihiko Matsuda, Tokyo, JP;
Assignee:
NIPPON MEKTRON, LTD., Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H01P 3/08 (2006.01); H01P 11/00 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0216 (2013.01); H01P 3/08 (2013.01); H01P 3/082 (2013.01); H01P 3/084 (2013.01); H01P 11/003 (2013.01); H05K 1/024 (2013.01); H05K 1/028 (2013.01); H05K 1/036 (2013.01); H05K 3/0014 (2013.01); H05K 3/0044 (2013.01); H05K 3/0052 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/09063 (2013.01); H05K 2203/107 (2013.01); Y10T 29/49165 (2015.01);
Abstract
The invention provides a method of manufacturing a printed circuit board. The printed circuit board () has a conductor layer (ground layer ()), a signal layer () having a signal line () provided so as to oppose the conductor layer (ground layer ()), and an insulating resin layer () disposed between the conductor layer (ground layer ()) and the signal layer (), the insulating resin layer () has voids in an overlapping location, in a plan view, with the signal line (), and the voids () are communicated with the outside of the printed circuit board ().