The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Sep. 22, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Vincent Loncke, Piscataway, NJ (US);
Girish Varatkar, Hillsborough, NJ (US);
Thomas Joseph Richardson, South Orange, NJ (US);
Yi Cao, Parsippany, NJ (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H04L 1/00 (2006.01); H03M 13/11 (2006.01); G06F 11/00 (2006.01); G06F 11/30 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0061 (2013.01); G06F 11/002 (2013.01); G06F 11/004 (2013.01); G06F 11/3006 (2013.01); H03M 13/114 (2013.01); H03M 13/116 (2013.01); H04L 1/00 (2013.01); H04L 1/0052 (2013.01); G06F 11/1443 (2013.01);
Abstract
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.