The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Oct. 23, 2019
Applicant:
Silicon Laboratories Inc., Austin, TX (US);
Inventors:
Aaron J. Caffee, Scappoose, OR (US);
Brian G. Drost, Corvallis, OR (US);
Assignee:
Silicon Laboratories Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/66 (2006.01); H03K 21/02 (2006.01);
U.S. Cl.
CPC ...
H03K 21/026 (2013.01); H03K 23/66 (2013.01); H03K 23/667 (2013.01);
Abstract
A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.