The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Aug. 28, 2019
Applicant:

Navitas Semiconductor, Inc., El Segundo, CA (US);

Inventors:

Santosh Sharma, Laguna Nigel, CA (US);

Marco Giandalia, Marina Del Rey, CA (US);

Daniel Marvin Kinzer, El Segundo, CA (US);

Thomas Ribarich, Laguna Beach, CA (US);

Assignee:

Navitas Semiconductor, Inc., El Segundo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01); H03K 17/687 (2006.01); H03K 3/037 (2006.01); H03K 19/0185 (2006.01); H02M 1/08 (2006.01); H01L 23/00 (2006.01); H02M 1/36 (2007.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H02M 1/08 (2013.01); H03K 3/037 (2013.01); H03K 19/018507 (2013.01); H01L 24/48 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/1426 (2013.01); H02M 1/36 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.


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