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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10777704 B1

PDFFull Text
Date of Patent:
Sep. 15, 2020

Filed:

Nov. 01, 2016

Manufacturing method for group iii nitride semiconductor substrate and group iii nitride semiconductor substrate

Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Koji Matsumoto, Tokyo, JP;

Toshiaki Ono, Tokyo, JP;

Hiroshi Amano, Aichi, JP;

Yoshio Honda, Aichi, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:

Greenblum & Bernstein, P.L.C.

Primary Examiner:

Ermias T Woldegeorgis

Int. Cl.
CPC ...
H01L 33/12 (2010.01); C23C 16/34 (2006.01); H01L 33/32 (2010.01); H01L 21/02 (2006.01); C30B 29/38 (2006.01); H01L 21/302 (2006.01); H01L 33/22 (2010.01); C30B 25/02 (2006.01); C30B 29/40 (2006.01); H01L 29/20 (2006.01); H01L 29/34 (2006.01); H01L 33/00 (2010.01); H01L 33/02 (2010.01);
U.S. Cl.
CPC ...
H01L 33/12 (2013.01); C23C 16/34 (2013.01); C30B 25/02 (2013.01); C30B 29/38 (2013.01); C30B 29/406 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02505 (2013.01); H01L 21/02639 (2013.01); H01L 21/02645 (2013.01); H01L 21/02647 (2013.01); H01L 21/302 (2013.01); H01L 29/2003 (2013.01); H01L 29/34 (2013.01); H01L 33/007 (2013.01); H01L 33/025 (2013.01); H01L 33/22 (2013.01); H01L 33/32 (2013.01); H01L 21/02488 (2013.01); H01L 21/02513 (2013.01);
Abstract

A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.

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