The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Nov. 14, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tomohiro Hayashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 27/1157 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42344 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/66833 (2013.01); H01L 29/785 (2013.01); H01L 29/7854 (2013.01);
Abstract

In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved. An insulating film is formed between an upper surface of a fin and each of a control gate electrode and a memory gate electrode in a memory cell region, so that in a gate insulating film of each of a control transistor and a memory transistor, thickness of a portion on the fin is larger than thickness of a portion covering side surfaces of the fin. The insulating film having a bird's beak at its end portion is formed to round a corner of the fin.


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