The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Feb. 13, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Teruyuki Ohashi, Kawasaki, JP;

Ryosuke Iijima, Setagaya, JP;

Hiroshi Kono, Himeji, JP;

Tatsuo Shimizu, Shinagawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/0465 (2013.01); H01L 29/0623 (2013.01); H01L 29/0646 (2013.01); H01L 29/086 (2013.01); H01L 29/0865 (2013.01); H01L 29/0869 (2013.01); H01L 29/0878 (2013.01); H01L 29/0882 (2013.01); H01L 29/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/42368 (2013.01); H01L 29/66068 (2013.01); H01L 29/66734 (2013.01); H01L 29/66348 (2013.01); H01L 29/7396 (2013.01); H01L 29/7397 (2013.01);
Abstract

A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.


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